module ALU(in1,in2,out,z_detect,aluOP);

input [7:0] in1,in2;

input [2:0] aluOP;

output z_detect;

output [7:0] out;


wire [7:0] r1,r2,r3,r4;
wire r5;
wire c1,c2,c3;//trash

and_8bit m1(in1,in2,r1);
or_8bit m2(in1,in2,r2);
add_sub_8bit m3(r3,c1,in1,in2,0,c2);  //add_sub_8bit(out,cout,in1,in2,M,slt);
add_sub_8bit m4(r4,c3,in1,in2,1,r5);

MUX8to1_1bit mx1(r1[0],r2[0],r3[0],0,r4[0],0,0,0,r5,out[0],aluOP,1);
MUX8to1_1bit mx2(r1[1],r2[1],r3[1],0,r4[1],0,0,0,0,out[1],aluOP,1);
MUX8to1_1bit mx3(r1[2],r2[2],r3[2],0,r4[2],0,0,0,0,out[2],aluOP,1);
MUX8to1_1bit mx4(r1[3],r2[3],r3[3],0,r4[3],0,0,0,0,out[3],aluOP,1);
MUX8to1_1bit mx5(r1[4],r2[4],r3[4],0,r4[4],0,0,0,0,out[4],aluOP,1);
MUX8to1_1bit mx6(r1[5],r2[5],r3[5],0,r4[5],0,0,0,0,out[5],aluOP,1);
MUX8to1_1bit mx7(r1[6],r2[6],r3[6],0,r4[6],0,0,0,0,out[6],aluOP,1);
MUX8to1_1bit mx8(r1[7],r2[7],r3[7],0,r4[7],0,0,0,0,out[7],aluOP,1);

nor n1(z_detect,out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]);

endmodule

module and_8bit(in_a1,in_a2,out_a);

input [7:0] in_a1,in_a2;
output [7:0] out_a;

and a01(out_a[0],in_a1[0],in_a2[0]);
and a02(out_a[1],in_a1[1],in_a2[1]);
and a03(out_a[2],in_a1[2],in_a2[2]);
and a04(out_a[3],in_a1[3],in_a2[3]);
and a05(out_a[4],in_a1[4],in_a2[4]);
and a06(out_a[5],in_a1[5],in_a2[5]);
and a07(out_a[6],in_a1[6],in_a2[6]);
and a08(out_a[7],in_a1[7],in_a2[7]);

endmodule

module or_8bit(in_o1,in_o2,out_o);

input [7:0] in_o1,in_o2;
output [7:0] out_o;

or o1(out_o[0],in_o1[0],in_o2[0]);
or o2(out_o[1],in_o1[1],in_o2[1]);
or o3(out_o[2],in_o1[2],in_o2[2]);
or o4(out_o[3],in_o1[3],in_o2[3]);
or o5(out_o[4],in_o1[4],in_o2[4]);
or o6(out_o[5],in_o1[5],in_o2[5]);
or o7(out_o[6],in_o1[6],in_o2[6]);
or o8(out_o[7],in_o1[7],in_o2[7]);

endmodule

module full_adder(out,cout,in1,in2,cin);

input in1;
input in2;
input cin;
output out;
output cout;

wire w1,w2,w3;

xor t1(w1,in1,in2);
xor t2(out,w1,cin);
and t3(w2,in1,in2);
and t4(w3,w1,cin);
or  t6(cout,w2,w3);

endmodule


module add_sub_8bit(out,cout,in1,in2,M,slt);

input [7:0] in1;
input [7:0] in2;
input M; //M=0 add M=1 sub

output [7:0] out;
output cout ;
output slt;

wire [7:0] w1,w2;

xor x1(w1[0],M,in2[0]);
xor x2(w1[1],M,in2[1]);
xor x3(w1[2],M,in2[2]);
xor x4(w1[3],M,in2[3]);
xor x5(w1[4],M,in2[4]);
xor x6(w1[5],M,in2[5]);
xor x7(w1[6],M,in2[6]);
xor x8(w1[7],M,in2[7]);

full_adder f1(out[0],w2[0],in1[0],w1[0],M);
full_adder f2(out[1],w2[1],in1[1],w1[1],w2[0]);
full_adder f3(out[2],w2[2],in1[2],w1[2],w2[1]);
full_adder f4(out[3],w2[3],in1[3],w1[3],w2[2]);
full_adder f5(out[4],w2[4],in1[4],w1[4],w2[3]);
full_adder f6(out[5],w2[5],in1[5],w1[5],w2[4]);
full_adder f7(out[6],w2[6],in1[6],w1[6],w2[5]);
full_adder f8(out[7],w2[7],in1[7],w1[7],w2[6]);


or sl(slt,0,out[7]);

endmodule

module MUX4to1_1bit(
  input0,
  input1,
  input2,
  input3,
  output0,
  sel,
  on
);

input input0, 
      input1,
      input2,
      input3;
input [1:0]sel;
input on;
output output0;

wire [3:0]w1;

and a0(w1[0], input0, ~sel[0], ~sel[1], on);
and a1(w1[1], input1, sel[0], ~sel[1], on);
and a2(w1[2], input2, ~sel[0], sel[1], on);
and a3(w1[3], input3, sel[0], sel[1], on);

or o0(output0, w1[0], w1[1], w1[2], w1[3]);

endmodule

module MUX8to1_1bit(
  input0,
  input1,
  input2,
  input3,
  input4,
  input5,
  input6,
  input7,
  output0,
  sel,
  on
);

input input0,
      input1,
      input2,
      input3,
      input4,
      input5,
      input6,
      input7;
input [2:0]sel;
input on;
output output0;


wire [1:0]w1;
wire [1:0]on1;
and a0(on1[0], ~sel[2], on);
and a1(on1[1], sel[2], on);

MUX4to1_1bit m0(input0, input1, input2, input3, w1[0], sel[1:0], on1[0]);
MUX4to1_1bit m1(input4, input5, input6, input7, w1[1], sel[1:0], on1[1]);

or o1(output0, w1[0], w1[1]);

endmodule

















